Founding build · 2026.3 · R2 bottom-up build · reviewed through August 30, 2026Independent · no vendor sponsorship
Fab Ledger
The supply side of memory, fab by fab.
A supply model of DRAM, HBM, and NAND bits through 2030. We compute it from 35 fab capacity blocks at 31 sites, starting with installed capacity, then wafer starts, then node mix, then sellable bits. Every number shows the disclosure, derivation, or assumption behind it. Published forecasts are shown next to ours and never mixed in.
Annual license, per firm · ten firms in the founding cohort · Joule14 replies within three business days
Where the next 31 exabytes come from6 makers · 31 sites · 35 capacity blocks · 96 data points
Sellable DRAM bits, 2024 to 2030E
×1.97
2026E bit growth · published median +25.1%
+13.3%
Commodity bits given up to HBM stacking, 2030E
−18 EB
Industry DRAM bit supply by source, 2024–2030EExabytes per year
Industry DRAM bit supply by source, 2024–2030EExabytes per year
2024 output Existing fabs (node migration, loading) New Korean fabs New US and Japanese fabs China HBM wafer drain Sellable bits, base case Published forecast, shipments basis
How to read a Joule14 number•Disclosed65ƒDerived11≈Assumed20○Reported77of 173Tier definitions
The summary · 2026.3 · R2 bottom-up build · as of September 2, 2026
Bits per wafer, not cleanrooms, set memory supply to 2030.
The answer
DRAM bit supply is 1.97 times its 2024 level by 2030, +12% a year on average. Growth slows from +20.6% in 2025 to +7.6% in 2030, apart from a step up in 2028 when new cleanrooms come on. NAND is 2.25 times its 2024 level by 2030.
DRAM bit supply growth by year, our model and the median of the published forecasts, 2025 to 2030
DRAM bit supply growth
2025
2026E
2027E
2028E
2029E
2030E
2024 to 2030
Our model
+20.6%
+13.3%
+9.5%
+11.1%
+10.3%
+7.6%
×1.97+12% a year
Published median
+21.9%2 organizations
+25.1%4 organizations
+23.3%3 organizations
+22%1 organization
+29.9%1 organization
+29%1 organization
two or more firms to 2027, one firm to 2030
Why it slows
HBM takes a rising share of the best wafers, 23.1% of DRAM wafer starts in 2026 and 30.5% by 2030, and each HBM wafer yields about a third of the bits. The cleanrooms that add new wafers (Idaho ID1, Yongin Fab 1 first phase, Hiroshima new building and P5 Phase 1) reach scale only from 2028.
Compared with published forecasts
For 2026, published forecasts say +25.1% (median of 4 organizations). Ours is +13.3%. We use the same wafer count and the same HBM bits, so all of the gap is in commodity bits per wafer, and no maker has disclosed a node step that large in one year. Past 2027 only one organization publishes a forecast (+22%, +29.9%, +29% for 2028 to 2030), on wafer capacity growing 17 to 18 percent a year. Our wafer starts grow about 4 percent a year over those years, and that is where the difference lies.
What will test it
The first test is Micron's fiscal Q4 2026 call in late September 2026. A calendar-2026 industry DRAM figure at or below +16% supports our number. One at or above the +25.1% median means our node schedules are too slow.
Checked against 2025 The model reproduces reported 2025 output within 0.7% for the industry and 2.6% for each maker (published vendor tables and the makers' calls through August 30, 2026).
The five findings behind this, each with what would prove it wrong
01
HBM takes 30.5% of DRAM wafer starts in 2030 and produces 16.1% of the bits.
Each HBM wafer yields about a third of the standard-equivalent bits at the 3.2× multiplier. HBM stacks take 705k wafer starts a month by 2030, up from 204k in 2024. Those wafers give up 22.5 EB of sellable supply that year, which is 26.2% of what the same wafers would ship as commodity DRAM. Node migration adds bits and HBM takes a rising share of them back. That pairing, not cleanroom space, sets the growth path.
HBM share of wafer starts, 2026 → 2030
23.1% → 30.5%ƒDerived
HBM share of bits, 2026 → 2030
10.8% → 16.1%ƒDerived
Bits given up to the multiplier, 2030
22.5 EB · 26.2% of output before the HBM penaltyƒDerived
HBM wafer multiplier, 2030
3.2׃Derived
What would change it An HBM4 trade ratio disclosed by a maker, a ten-point gain in known-good-stack yield, or HBM demand guidance that lowers the wafer share below the block schedules.
57.2% of the gross DRAM bits added by 2030 come from node migration inside cleanrooms that already exist. New cleanrooms add 17.7 EB, China 3.5 EB, and HBM takes 18.4 EB back.
Existing fabs add 28.4 EB through node migration and conversion. New Korean cleanrooms add 14.0 EB. US and Japanese greenfield adds 3.7 EB. China adds 3.5 EB. The HBM drain takes 18.4 EB back, for a net 31.3 EB on the 2024 base. The added bits come from density gains, and new wafers add to them only from 2028.
Existing fabs, 2030
28.4 EBƒDerived
New Korean cleanrooms, 2030
14.0 EBƒDerived
US and Japan greenfield, 2030
3.7 EBƒDerived
China, 2030
3.5 EBƒDerived
HBM drain, 2030
−18.4 EBƒDerived
What would change it A maker pausing conversions to protect HBM output, or a greenfield block disclosing first output earlier than the date in our model.
New DRAM cleanrooms come in two waves. P4 Phase 2, M15X and P4 Phases 3–4 provide the new capacity from 2025 to 2027. Idaho ID1, Yongin Fab 1 first phase, Hiroshima new building and P5 Phase 1 reach 20k wafer starts a month only from 2028.
The first wave runs 148k of new-cleanroom wafer starts a month by 2027. The second adds 154k more by 2030. Between the waves, wafer growth comes from expansions inside existing sites and from China. So the 2028 to 2030 wafer path rests on 4 fab capacity blocks whose first-output dates are the least-disclosed inputs in the model, and every one of them is a block we have assumed.
P4 Phase 2, 20k starts from
2025 · 64k at peak≈Assumed
M15X, 20k starts from
2026 · 83k at peak≈Assumed
P4 Phases 3–4, 20k starts from
2027 · 64k at peak≈Assumed
Idaho ID1, 20k starts from
2028 · 42k at peak≈Assumed
Yongin Fab 1 first phase, 20k starts from
2029 · 49k at peak≈Assumed
Hiroshima new building, 20k starts from
2029 · 21k at peak≈Assumed
P5 Phase 1, 20k starts from
2030 · 42k at peak≈Assumed
What would change it A restated first-output date for any of these blocks, a cleanroom completion disclosed ahead of plan, or a tool-order cycle that shortens our ramp rule.
CXMT reaches 14.4% of the industry's DRAM wafers by 2030 but 8.3% of its bits. The tool gap, not the cleanroom, sets the bit share.
Our base case holds CXMT to 310k installed in 2027, compared with a published 370k, median of 2 organizations · 360k to 380k. The unconstrained scenario matches the published forecast at 379k and adds 1.5 EB in 2030. The tool-constrained case removes 2.1 EB. CXMT's bits per wafer run at 57.2% of the industry average in 2030 because its node ladder stops near 1α-equivalent without EUV, so every added Chinese wafer holds fewer bits than the wafer it competes with.
CXMT share of DRAM wafers, 2030
14.4%ƒDerived
CXMT share of DRAM bits, 2030
8.3%ƒDerived
CXMT installed capacity, 2027, base
310k a month≈Assumed
CXMT wafer capacity, 2027, published
370k, median of 2 organizations · 360k to 380k a month○Reported
What would change it Observed immersion-DUV or etch tool imports above the base schedule, a CXMT listing disclosure of installed capacity, or a node announcement below 1α-equivalent in volume.
NAND grows +22% in 2026 with only 8.6% more wafers than in 2024. Added layers produce that growth, and the reported +21.1% for 2027 needs a density step that the conversions do not produce.
Wafer starts move from 1,309k in 2024 to 1,422k in 2026, while bits per wafer rise +16.8% on conversions from 2xx to 3xx layers and a rising QLC share. The published forecast has wafers out moving −2.7% in 2027 with bits up +21.1%, which needs +24.5% more bits per wafer in one year. In our model the conversions produce +11.7%, with Kitakami K2 and YMTC adding wafers, for +14.3% growth in 2027.
2026 NAND bit growth, Fab Ledger
+22%ƒDerived
2026 NAND bit growth, published
+19.1%, median of 3 organizations · +17% to +20%○Reported
2027 NAND bit growth, Fab Ledger
+14.3%ƒDerived
2027 NAND bit growth, published
+21.1% · 1 organization○Reported
Bits per wafer, 2027 growth
+11.7% our figure · +24.5% implied by the published forecastƒDerived
What would change it A maker disclosing a 4xx-layer crossover earlier than our layer ladder, QLC above half of starts, or wafer cuts deeper than the utilization path.
Its statement of calendar-2026 industry DRAM bit growth. Our figure is +13.3%. The lowest published forecast we have found is +16%. A statement at or below that supports our figure. One at or above the +25.1% median means our node schedules are too slow.
Samsung's and SK hynix's third-quarter results
Quarter-on-quarter DRAM bit growth. Our +13.3% for the year is about +3.2% a quarter. Two second-half results well above that, without an inventory drawdown behind them, move our 2026 figure up.
Samsung's HBM4 qualification
Our model has Samsung's HBM wafers at 1.8× the industry multiplier in 2025, closing to 1.2× in 2026 as HBM4 qualifies. A slip keeps the wafer drain and lowers HBM bits. It does not raise commodity supply.
A maker discloses an HBM4 trade ratio
The multiplier path (3.1× in 2026) is the assumption with the least disclosure behind it. A +0.5× change moves 2026 growth 1.7 points lower.
Where the bits come from
Node migration adds ten points. HBM takes five back.
Bit supply is wafer starts times bits per wafer. Installed capacity × utilization gives wafer starts. The node mix gives bits per wafer. The product mix decides how many of those wafers go into HBM stacks, which in 2026 give 10.8% of bits for 23.1% of wafers. The bridge below shows where 2026 DRAM growth comes from, one step at a time, with how well each step is backed up. The steps add up to the base case, and what is left over is rounding.
Industry DRAM2025 → 2026 · percentage points of bit growth · each step added in order
Node migration (bits per wafer)≈Assumed6 points · 3/2/1
+9.6 pts
Each fab capacity block's node mix moves to its 2026 schedule, with wafer starts held at 2025 levels. Blended good bits per wafer go from 2.14 TB to 2.35 TB, before the product-mix effect.
Installed capacity≈Assumed12 points · 7/3/1/1
+5.3 pts
Installed capacity goes from 1971k to 2093k wpm, at 2025 utilization. The largest moves are Beijing fab +40k, P4 Phase 2, DRAM +35k, M15X +25k, M16 (phases 1–2) +20k, Hefei Fab 1 and Fab 2 +10k.
Utilization≈Assumed3 points · 0/0/3
+3 pts
Wafer starts as a share of installed capacity go from 91% to 93%.
HBM wafer drain and multiplierƒDerived6 points · 3/2/1
-4.6 pts
HBM goes from 7.3% to 10.8% of bits (321k to 449k wafer starts), with the multiplier moving from 3× to 3.1×.
NAND
Layers add fifteen points. Wafers add one.
NAND wafers barely move. Conversions to 3xx-layer generations use up floor space, Kitakami K2 and YMTC add a little, and loading recovers from the 2025 cuts. The bits come from layers and the QLC share of starts. We use the same blocks and the same model as for DRAM, and we mark how well each number is backed up in the same way.
Industry NAND bit supply by source, 2024–2030EExabytes per year
2024 output Existing fabs (node migration, loading) New Korean fabs New US and Japanese fabs China HBM wafer drain Sellable bits, base case Published forecast, shipments basis
Industry NAND2025 → 2026 · percentage points of bit growth · each step added in order
Layer migration (bits per wafer)≈Assumed5 points · 4/0/1
+14.5 pts
Each fab capacity block's node mix moves to its 2026 schedule, with wafer starts held at 2025 levels. Blended good bits per wafer go from 62.5 TB to 73 TB, before the product-mix effect.
Installed capacity≈Assumed10 points · 8/0/2
+1.2 pts
Installed capacity goes from 1714k to 1728k wpm, at 2025 utilization. The largest moves are Kitakami K2 +15k, Wuhan Fab 1–3 +15k, Yokkaichi Fabs 2–7 −5k, Pyeongtaek P1/P2 NAND −4k, Singapore Fab 10 −2k.
Utilization≈Assumed3 points · 2/0/1
+4.2 pts
Wafer starts as a share of installed capacity go from 79% to 82%.
QLC mixƒDerived2 points · 1/0/1
+2.2 pts
Bits per wafer rise as the QLC share of wafer starts rises.
The series as tables
Industry DRAM bit supply by year: index, growth, band, and HBM share
Measure
Backed by
2024
2025
2026E
2027E
2028E
2029E
2030E
Output
Bit supply index2024 = 100
ƒDerived
100
120.6
136.6
149.6
166.2
183.2
197.2
Year-on-year growthpercent
ƒDerived
—
+20.6%
+13.3%
+9.5%
+11.1%
+10.3%
+7.6%
Low–high bandindex, from four re-runs of the model
≈Assumed
—
—
126.5–142.5
135.2–157.4
147.5–174
161.5–189.2
172.7–201.1
Growth rangepercent, from four re-runs of the model
The model computes the reported years from the fab capacity blocks in the same way as every other year. The licensed version of this table adds these rows: sellable exabytes, installed capacity, utilization, wafer starts, bits per wafer, HBM wafer starts and bits, by year and by maker.
Industry NAND bit supply by year: index, growth, and band
Measure
Backed by
2024
2025
2026E
2027E
2028E
2029E
2030E
Output
Bit supply index2024 = 100
ƒDerived
100
119.9
146.2
167.1
190.3
208.9
224.9
Year-on-year growthpercent
ƒDerived
—
+19.9%
+22%
+14.3%
+13.8%
+9.8%
+7.6%
Low–high bandindex, from four re-runs of the model
≈Assumed
—
—
135.6–155.7
151.3–177.5
170–199.5
184.6–220.1
198.3–238.5
Growth rangepercent, from four re-runs of the model
The model computes the reported years from the fab capacity blocks in the same way as every other year. The licensed version of this table adds these rows: sellable exabytes, installed capacity, utilization, wafer starts, bits per wafer, HBM wafer starts and bits, by year and by maker.
Where our figures differ from published forecasts, and why.
The published forecasts are the industry supply figures (bit supply growth, wafers out, wafer capacity growth, the HBM share of bits, CXMT capacity) that 8 organizations (UBS Global Research, LS Securities, TrendForce, Micron Technology, IDC, J.P. Morgan, Daishin Securities, and SemiAnalysis) have published and that we have read in the original documents. For each measure and year we take the median of one figure per organization and show the range and the count. Nothing is surveyed or taken from a data vendor's feed. The figures behind the 2026 DRAM median and behind each gap of three points or more are listed below with their organization, value, and date. The full register of published figures is in the licensed workspace. Published figures are marked reported, a label of their own in Fab Ledger. We show them in grey, keep them in a count of their own, and never use them as an input.
The table covers every supply measure we track through 2030 and marks each cell where no forecast is published. The breakdown under it shows where the disagreement comes from, and the folds explain the gaps that matter with the fab capacity blocks that account for them.
Who publishes a forecast for 2028 to 2030 Published supply forecasts thin out after 2027. Of the 5 organizations we count, only one publishes a figure for 2028 to 2030: DRAM bits up +22%, +29.9%, +29% in its August 2026 report, with wafer capacity growing 17 to 18 percent a year as the new fabs fill. The other 4 stop at 2027. One figure (for 2028) could only be read second-hand and is listed but not counted. So for 2028 to 2030 the published figure is one organization's model, and we show it as such. Our figures for those years are +11.1%, +10.3%, +7.6%. The difference is wafers rather than bits per wafer: our installed capacity grows about 5 percent a year and our wafer starts about 4 percent a year over 2028 to 2030, because the new cleanrooms fill more slowly in our schedules. What is published to 2030 by more organizations (3 of them) is demand. Demand is a different measure, and we keep it off these supply pages.
Our figures compared with the published supply forecasts, by measure and year
Our figure in bold. Below it is the median of the published forecasts we have collected, with the number of organizations included in the median.The gap is our figure minus that median. Cells are shaded where the gap is beyond three points. "no published supply forecast" marks a year that no organization in our records publishes a figure for. "from a multi-year growth rate" marks a year whose figure comes from a published multi-year growth rate spread across its years.
Why the gap is bits per wafer
DRAM bit supply reaches 1.97 times its 2024 level by 2030, growing +13.3% in 2026 and about +9.6% a year after that. That is below every published 2026 figure we have found, 3 points under the lowest and 12 under the median. The published forecasts need commodity bits per wafer that the fabs cannot produce.
When we break the published forecast into the same parts as our model, the published forecast and our model agree on the two parts that makers disclose. Wafers out are 1,944k a month in our model and 1,921k in the published forecast for 2026, +1.2% apart. HBM bits are 4.8 EB in our model and 4.6 EB in the published forecast, with HBM near 23.1% of wafers in both (the published forecast has 22.2%). Everything left is commodity bits per wafer. The published forecast needs +21.6% in 2026 and +16.2% again in 2027, after about +8.9% in 2025. The fab capacity blocks produce +7.1%, because node migration adds +9.6 pts in the 2026 bridge (the bridge shows where each year's growth comes from) and HBM, at 23.1% of wafer starts, takes −4.6 pts back. No maker has disclosed a node step that large across all of its fabs in one year. The timing of the HBM wafer shift is the largest risk we have identified to our own figure. Our base case uses the published 2025 share (about 18% of wafers). If the shift landed a year later, more of it would fall in 2026 and our figure would come out at +10.5%. Growth settles near +9.6% because the second wave of new cleanrooms reaches 20k wafer starts a month only from 2028 and the node ladder flattens after 1c.
2026 DRAM bit growth, Fab Ledger
+13.3%ƒDerived
2026 DRAM bit growth, published
+25.1%, median of 4 organizations · +16% to +32.2% · our figure minus this median: −11.8 pts○Reported
2027–2030 DRAM bit growth a year, our figure · published
+9.6% · +26.1%○Reported
2026 wafers out, Fab Ledger
1,944k a monthƒDerived
2026 wafers out, published
1,921k · 1 organization a month○Reported
2026 HBM bits, our figure · published
4.8 EB · 4.6 EBƒDerived
Commodity bits per wafer, 2026 growth
+7.1% our figure · +21.6% in the published forecastƒDerived
Commodity bits per wafer, 2025 growth, our figure
+8.9%ƒDerived
What would change it A maker disclosing 1c good bits per wafer above the node table, an HBM wafer share below 15% in 2026, evidence that HBM's wafer share had already reached the published 18% in 2025, or a reported bit-shipment figure that includes 2025 inventory carried into 2026 rather than new output.
Our figures compared with the published forecast on the three terms that make the argument, 2025 to 2027
DRAM · our figures compared with the published forecast
2025
2026E
2027E
About the published figure
DRAM wafers out, k a month
1,788k1,784k
1,944k1,921k
2,046k2,119k
taken from the report
HBM bits, EB
2.862.69
4.754.58
6.516.72
taken from the report: HBM bit shipments
Commodity bits per wafer, growth
+8.9%+5.5%
+7.1%+21.6%
+6.4%+16.2%
derived the same way as our figure. For 2025 we use the 2024 year-end HBM share as the 2024 average
Our figure in bold, with the published forecast beneath it. One organization publishes wafers out, HBM bit shipments, and total supply together, so it is the only published forecast we can split this way. The marked row is where the two disagree.
The full breakdown, and the same comparison by maker, is in the licensed workspace.
The figures behind the 2026 DRAM median: 4 organizations counted, with the second-hand figures listed beside them
Every published figure we have collected is a dated entry with its exact quote, its basis (supply, shipments, or demand), and how we read its text. We mark a figure primary when we read the organization's own document, quoted when we found its sentence word for word inside another document, and paraphrased when we could only reach a third party's summary. For each measure and year the published forecast is the median of one primary or quoted figure per organization. The latest statement from each organization replaces its earlier ones. We show the range and the number of sources. Paraphrased figures are listed next to the median but not included in it. We mark research houses and banks reported. We take a maker's statement about the industry from its own earnings call.
UBS Global Researchprimary+27.2%shipments basis · 2026-08-30
LS Securitiesprimary+32.2%capacity basis · 2026-08-25
Micron Technologyquoted+21% to +25%shipments basis · 2026-06-24
IDCprimary+16%supply basis · 2025-12-18
Morgan Stanleyparaphrasednot in the median+15% to +20%supply basis · 2026-06-20
Morgan Stanleyparaphrasednot in the median+29%supply basis · 2026-06-02
TrendForceparaphrasednot in the median+16%supply basis · 2026-02-02
Checked against 2025, by maker
The only check we can run on a forecast is whether the model reproduces the last reported year. We set the 2024 base and 2025 growth so the model reproduces the reported bits, wafers, and HBM bits for each maker. From 2026 onward the figures are model output from the node roadmaps the makers have disclosed. The differences that remain are printed here.
Our figures compared with reported figures by maker, 2024 and 2025
Maker · year
Bits, EB
Gap
Wafers out, k wpm
Gap
HBM bits, EB
Bit growth
2024 · our figures compared with reported figures
Industry
32.2332.66
−1.3%
1,567k1,558k
+0.6%
1.52—
——
SK hynix
9.069.36
−3.2%
439k—
—
0.86—
——
Samsung
12.8913.71
−6%
585k—
—
0.37—
——
Micron
7.557.55
0%
292k—
—
0.28—
——
CXMT
1.721.57
+9.6%
152k—
—
0.00—
——
Others
1.010.43
+134.9%
99k—
—
0.00—
——
2025 · our figures compared with reported figures
Industry
38.8739.15
−0.7%
1,788k1,784k
+0.2%
2.862.69
+20.6%+19.9%
SK hynix
11.3311.63
−2.6%
513k509k
+0.8%
1.611.58
+25.1%+24.3%
Samsung
14.7715.03
−1.7%
658k668k
−1.5%
0.590.54
+14.5%+9.7%
Micron
9.009.20
−2.2%
313k312k
+0.3%
0.660.57
+19.2%+21.8%
CXMT
2.612.62
−0.4%
197k190k
+3.7%
0.00—
+51.7%+67.5%
Others
1.160.67
+73.1%
107k57k
+87.7%
0.00—
+15%+54.3%
Our figure in bold, with the reported figure beneath it. We mark gaps beyond five percent. The reported 2024 figures are the 2025 figures with the reported 2025 growth taken out. The reported line for the trailing makers (Nanya, Winbond and PSMC) is Nanya alone.
The 27 rows where the gap is three points or more, each explained with its sources
DRAM bit supply growth, 2026+13.3%compared with +25.1%, median of 4 organizations · +16% to +32.2%−11.8 pts
Wafer counts agree within three points. Our figure is 1,944k wafers started. The median of the published forecasts is 1,921k wafers out. To reach the median published forecast, bits per wafer out would need to grow +16.2% in 2026. Our fab capacity blocks produce +4.2%, made up of +9.6 pts from node migration and −4.6 pts from the HBM wafer drain in our 2026 bridge, the breakdown of where that year's growth comes from. A shipments series also includes inventory movements, which a production series does not.
DRAM bit supply growth, 2027+9.5%compared with +23.3%, median of 3 organizations · +20% to +25%−13.8 pts
Wafer counts differ. Our figure is 2,046k wafers started. The median of the published forecasts is 2,119k wafers out. To reach the median published forecast, bits per wafer out would need to grow +11.8% in 2027. Our fab capacity blocks produce +4%, made up of +7.6 pts from node migration and −3.1 pts from the HBM wafer drain in our 2027 bridge, the breakdown of where that year's growth comes from. A shipments series also includes inventory movements, which a production series does not.
DRAM bit supply growth, 2028+11.1%compared with +22% · 1 organization−10.9 pts
Our fab capacity blocks produce +6.1% growth in bits per wafer out, made up of +7.1 pts from node migration and −1.2 pts from the HBM wafer drain. A shipments series also includes inventory movements, which a production series does not.
DRAM bit supply growth, 2029+10.3%compared with +29.9% · 1 organization−19.6 pts
Our fab capacity blocks produce +6.1% growth in bits per wafer out, made up of +6.5 pts from node migration and −0.7 pts from the HBM wafer drain. A shipments series also includes inventory movements, which a production series does not.
DRAM bit supply growth, 2030+7.6%compared with +29% · 1 organization−21.4 pts
Our fab capacity blocks produce +3.8% growth in bits per wafer out, made up of +4.2 pts from node migration and −0.7 pts from the HBM wafer drain. A shipments series also includes inventory movements, which a production series does not.
DRAM bits per wafer out, 2026 growth+4.2%compared with +16.2% implied by the median published forecasts for supply and wafersAll of the gap is here
Our node migration step is +9.6 pts and our HBM wafer drain is −4.6 pts. The figure implied by the published forecasts would need every leading-node wafer to ship as commodity bits. The licensed version of Fab Ledger breaks this row down by node and by fab.
UBS Global Research+27.2%
LS Securities+32.2%
Micron Technology+21% to +25%
IDC+16%
Morgan Stanleynot in the median+15% to +20%
Morgan Stanleynot in the median+29%
TrendForcenot in the median+16%
sec-p3-dramskh-m16-drammu-taichung-dram
DRAM bits per wafer out, 2027 growth+4%compared with +11.8% implied by the median published forecasts for supply and wafersAll of the gap is here
Our node migration step is +7.6 pts and our HBM wafer drain is −3.1 pts. The figure implied by the published forecasts would need every leading-node wafer to ship as commodity bits. The licensed version of Fab Ledger breaks this row down by node and by fab.
UBS Global Research+23.3%
LS Securities+24%
Daishin Securities+20% to +25%
Barclaysnot in the median+20%
sec-p3-dramskh-m16-drammu-taichung-dram
DRAM wafers out, 2027 (k wpm)2,046kcompared with 2,119k · 1 organization−3.4%
Our model and the published forecasts count different fabs or different loadings. Installed capacity goes from 2093k to 2202k wpm, at 2026 utilization. The largest moves are M15X +40k, P4 Phases 3–4, DRAM +30k, M16 (phases 1–2) +10k, P4 Phase 2, DRAM +10k, Hefei Fab 1 and Fab 2 +10k.
UBS Global Research2,119k
J.P. Morgannot in the median2,290k
skh-m15x-dramsec-p4-ph2-dramcxmt-beijing-dram
DRAM wafer capacity, growth, 2026+6.2%compared with +12.9% · 1 organization−6.7 pts
Both figures are installed wafer capacity, so they are on the same basis. Our fab capacity blocks have 2,093k a month installed in 2026 against 1,971k in 2025. The published figure adds the new fabs on the publisher's own schedule. The difference is how fast the new cleanrooms fill.
DRAM wafer capacity, growth, 2027+5.2%compared with +14.6% · 1 organization−9.4 pts
Both figures are installed wafer capacity, so they are on the same basis. Our fab capacity blocks have 2,202k a month installed in 2027 against 2,093k in 2026. The published figure adds the new fabs on the publisher's own schedule. The difference is how fast the new cleanrooms fill.
DRAM wafer capacity, growth, 2028+5.3%compared with +16.6% · 1 organization−11.3 pts
Both figures are installed wafer capacity, so they are on the same basis. Our fab capacity blocks have 2,319k a month installed in 2028 against 2,202k in 2027. The published figure adds the new fabs on the publisher's own schedule. The difference is how fast the new cleanrooms fill.
DRAM wafer capacity, growth, 2029+4.7%compared with +18.1% · 1 organization−13.4 pts
Both figures are installed wafer capacity, so they are on the same basis. Our fab capacity blocks have 2,428k a month installed in 2029 against 2,319k in 2028. The published figure adds the new fabs on the publisher's own schedule. The difference is how fast the new cleanrooms fill.
DRAM wafer capacity, growth, 2030+4.5%compared with +17.3% · 1 organization−12.8 pts
Both figures are installed wafer capacity, so they are on the same basis. Our fab capacity blocks have 2,537k a month installed in 2030 against 2,428k in 2029. The published figure adds the new fabs on the publisher's own schedule. The difference is how fast the new cleanrooms fill.
In our base case, CXMT is limited to what domestic tools and its pre-control DUV inventory can equip. The unconstrained scenario on the CXMT record has 195k installed in 2024, which matches the published path.
UBS Global Research205k
cxmt-hefei-dramcxmt-beijing-dram
CXMT wafer capacity, 2025 (k wpm)240kcompared with 260k, median of 2 organizations · 240k to 280k−7.7%
In our base case, CXMT is limited to what domestic tools and its pre-control DUV inventory can equip. The unconstrained scenario on the CXMT record has 267k installed in 2025, which matches the published path.
UBS Global Research240k
LS Securities280k
cxmt-hefei-dramcxmt-beijing-dram
CXMT wafer capacity, 2027 (k wpm)310kcompared with 370k, median of 2 organizations · 360k to 380k−16.2%
In our base case, CXMT is limited to what domestic tools and its pre-control DUV inventory can equip. The unconstrained scenario on the CXMT record has 379k installed in 2027, which matches the published path.
In our base case, CXMT is limited to what domestic tools and its pre-control DUV inventory can equip. The unconstrained scenario on the CXMT record has 419k installed in 2028, which matches the published path.
In our base case, CXMT is limited to what domestic tools and its pre-control DUV inventory can equip. The unconstrained scenario on the CXMT record has 447k installed in 2029, which matches the published path.
In our base case, CXMT is limited to what domestic tools and its pre-control DUV inventory can equip. The unconstrained scenario on the CXMT record has 475k installed in 2030, which matches the published path.
LS Securities600k
cxmt-hefei-dramcxmt-beijing-dram
NAND bit supply growth, 2025+19.9%compared with +15.4% · 1 organization+4.5 pts
Our figure comes from layer migration and loading (+13.1 pts from layer migration, +4.6 pts from loading, +2.2 pts from QLC mix).
UBS Global Research+15.4%
sec-pyeongtaek-nandkx-yokkaichi-nandskh-m15-nand
NAND bit supply growth, 2027+14.3%compared with +21.1% · 1 organization−6.8 pts
To reach the median published forecast using the published wafer count, bits per wafer out would need to grow +24.5% in 2027. Our fab conversions produce +11.7% (+9.6 pts from layer migration, +1.3 pts from loading, +1.8 pts from QLC mix).
Our model and the published forecasts count different fabs or different loadings. Installed capacity goes from 1714k to 1728k wpm, at 2025 utilization. The largest moves are Kitakami K2 +15k, Wuhan Fab 1–3 +15k, Yokkaichi Fabs 2–7 −5k, Pyeongtaek P1/P2 NAND −4k, Singapore Fab 10 −2k.
Our model and the published forecasts count different fabs or different loadings. Installed capacity goes from 1728k to 1751k wpm, at 2026 utilization. The largest moves are Kitakami K2 +25k, Wuhan Fab 1–3 +15k, Yokkaichi Fabs 2–7 −6k, Pyeongtaek P1/P2 NAND −4k, Singapore Fab 10 −2k.
HBM bit growth, 2026+66.3%compared with +77.5%, median of 2 organizations · +70% to +85% · 1 from multi-year growth rates−11.2 pts
Our HBM bits come from the HBM wafer starts in the fab capacity blocks, converted with the HBM wafer multiplier. The published figure is a shipments or demand forecast. 1 of the 2 figures included in this median are multi-year growth rates spread evenly across the years of the span, including this year. A published compound annual growth rate does not say how growth is shaped inside its span. So the median for this year is the level that the published path averages to. It is not a forecast for this year.
DRAM wafers out, growth, 2027+5.2%compared with +10.3% · 1 organization−5.1 pts
In our model, wafer growth comes from installed capacity and utilization in the fab capacity blocks. Installed capacity goes from 2093k to 2202k wpm, at 2026 utilization. The largest moves are M15X +40k, P4 Phases 3–4, DRAM +30k, M16 (phases 1–2) +10k, P4 Phase 2, DRAM +10k, Hefei Fab 1 and Fab 2 +10k.
UBS Global Research+10.3%
Barclaysnot in the median+18%
skh-m15x-dramsec-p4-ph2-dramcxmt-beijing-dram
HBM bit growth, 2027+37.1%compared with +50%, median of 3 organizations · +46.7% to +85% · 1 from multi-year growth rates−12.9 pts
Our HBM bits come from the HBM wafer starts in the fab capacity blocks, converted with the HBM wafer multiplier. The published figure is a shipments or demand forecast. 1 of the 3 figures included in this median are multi-year growth rates spread evenly across the years of the span, including this year. A published compound annual growth rate does not say how growth is shaped inside its span. So the median for this year is the level that the published path averages to. It is not a forecast for this year.
HBM bit growth, 2028+22.4%compared with +85% · 1 organization, multi-year growth rate−62.6 pts
Our HBM bits come from the HBM wafer starts in the fab capacity blocks, converted with the HBM wafer multiplier. The published figure is a shipments or demand forecast. Every figure included in this median is a multi-year growth rate spread evenly across the years of the span, including this year. A published compound annual growth rate does not say how growth is shaped inside its span. So the median for this year is the level that the published path averages to. It is not a forecast for this year.
HBM share of DRAM wafers, 202413%compared with 15.6% · 1 organization−2.6 pts
CXMT share of DRAM bits, 20245.3%compared with 5% · 1 organization+0.3 pts
DRAM wafers out, growth, 2025+14.1%compared with +14.5% · 1 organization−0.4 pts
HBM share of DRAM wafers, 202517.9%compared with 19.1%, median of 2 organizations · 18% to 20.2%−1.2 pts
CXMT share of DRAM bits, 20256.7%compared with 7% · 1 organization−0.3 pts
DRAM wafers out, growth, 2026+8.7%compared with +7.7% · 1 organization+1 pts
HBM share of DRAM wafers, 202623.1%compared with 24%, median of 3 organizations · 22% to 24.3%−0.9 pts
CXMT share of DRAM bits, 20268.4%compared with 8% · 1 organization+0.4 pts
HBM share of DRAM wafers, 202727.2%compared with 29.6%, median of 2 organizations · 29.1% to 30%−2.4 pts
CXMT share of DRAM bits, 20278.7%compared with 9% · 1 organization−0.3 pts
HBM share of DRAM wafers, 202828.8%compared with 31% · 1 organization−2.2 pts
Fab records
31 sites and 35 fab capacity blocks, one record each.
Each record separates what the maker disclosed from what we modeled, block by block. A block is a phase, a cleanroom, or a capacity block with its own paths for installed capacity, utilization, node mix, and product mix. One record is opened below to show the full chain from installed wafers to sellable bits. The rest are rows in the register until a license is in place. We do not model Nanya Technology, Winbond, PSMC site by site. They are in the industry baseline.
SK hynix · DRAM wafers
M15X
Cheongju, North Chungcheong, Korea · 1b / 1c DRAM for HBM3E and HBM4
Ramping▮▮▯medium
Investment •Disclosed
₩5.3T shell; >₩20T long-term
Wafer starts ≈Assumed
≈80k wpm at full ramp
Capacity blocks ≈Assumed
Block
First year adding supply
Peak starts
+EB by 2030
M15X Ramping
2026
83k wpm
+1.63
Installed → started → shipped, by year
Year
2024
2025
2026E
2027E
2028E
2029E
2030E
Installed, k wpm
0
0
25
65
85
88
90
Wafer starts, k wpm
0
0
21
59
77
80
83
Sellable bits, EB
0.00
0.00
0.37
1.04
1.43
1.53
1.63
Node mix of starts
2024
2026skh-1c 80% · skh-1b 20%
2028skh-1c 50% · skh-1d 50%
2030skh-1d 50% · skh-0a 35% · skh-1c 15%
Product mix of starts
2024
2026HBM 80% · DDR 18%
2028HBM 83% · DDR 16%
2030HBM 85% · DDR 14%
Construction start•Disclosed
Building completion (target)•Disclosed
Tool move-in and initial output≈Assumed
Full run rate≈Assumed
Our model's contribution ≈Assumed
We model this fab at 83k wpm of wafer starts at peak on 1c-class 24Gb from 1H 2026, reaching full run rate 2H 2027. At 80k wpm on a 1c-class die, the site produces roughly 2.6 EB per year of standard-DRAM-equivalent bits, or about 0.8 EB of shipped HBM bits once the ≈3.2× wafer multiplier is applied. That is close to 6% of 2026 industry DRAM wafer capacity.
The shell and timeline are disclosed. Wafer starts and node mix are not. We expect most M15X wafers to feed HBM, so its contribution to standard DRAM bits is small even at full ramp.
SourcesSK hynixSK hynix to build new DRAM production base M15X in CheongjuApr 24, 2024 · Newsroom release on construction budget, timeline, and HBM focusNewsroom, opens in a new tab
When each block starts affecting supply
New and expanding fab capacity blocks, by the year each one starts adding supply
Fab capacity blocks by the year they start adding supply
Block
Kind
2025
2026E
2027E
2028E
2029E
2030E
Hefei DRAM fabs · Hefei Fab 1 and Fab 2CXMT · China · ≈Assumed
Expansion
M16 · M16 (phases 1–2)SK hynix · Korea · ≈Assumed
Expansion
Pyeongtaek P3 · P3, DRAM linesSamsung · Korea · ≈Assumed
Expansion
Wuhan NAND fabs · Wuhan Fab 1–3YMTC · China · ≈Assumed
Idaho ID2 · Idaho ID2Micron · United States · ≈Assumed
New
New York megafab, Fab 1 · New York Fab 1Micron · United States · ≈Assumed
New
For the opened fab records, the values are the extra exabytes added on top of 2024. The other rows show only the year the block starts adding supply. NAND rows use the same units (exabytes) and come out larger than DRAM rows.
Fab register: the sites that add output before 2030 or are converting or paused, with status, next milestone, capacity blocks, wafer starts, and evidence count
Maker
Site
Status
Next milestone
Blocks · first year
Wafer starts · licensed
Evidence
Adding output before 2030 17
CXMT
Beijing fabBeijing, China · DRAM wafers
Ramping
2026–2027Ramp
12025
≈Assumedwithheld
2 points · 1 sources▮▯▯low
CXMT
Hefei DRAM fabsHefei, Anhui, China · DRAM wafers
Ramping
2026Hefei run rate at the company-wide target
12025
≈Assumedwithheld
3 points · 1 sources▮▯▯low
SK hynix
M15XCheongju, North Chungcheong, Korea · DRAM wafers
Ramping
2H 2027Full run rate
12026
≈80k wpm at full ramp≈Assumed
5 points · 1 sources▮▮▯medium
YMTC
Wuhan NAND fabsWuhan, Hubei, China · NAND wafers
Ramping
2025–2026Fab 3 expansion with domestic tools
12025
≈Assumedwithheld
2 points · 1 sources▮▯▯low
Kioxia/Sandisk
Kitakami K2Kitakami, Iwate, Japan · NAND wafers
Equipping
2029Full fill on BiCS10
22025 · 2026
≈Assumedwithheld
5 points · 1 sources▮▮▯medium
Micron
Hiroshima fab and new buildingHigashihiroshima, Hiroshima, Japan · DRAM wafers
Equipping
2H 2027New building output
22025 · 2027
≈Assumedwithheld
2 points · 2 sources▮▮▯medium
Samsung
Cheonan and Onyang HBM packagingCheonan, South Chungcheong, Korea · HBM packaging
Equipping
1H 2026HBM4 stacking lines
—
Packaging and test, so no wafer starts
1 points · 1 sources▮▮▯medium
Samsung
Pyeongtaek P4Pyeongtaek, Gyeonggi, Korea · DRAM + NAND wafers
Equipping
2026–2028Phases 3–4: 1c DRAM/HBM4 and V9/V10 NAND
22025 · 2027
≈Assumedwithheld
6 points · 1 sources▮▯▯low
Micron
Idaho ID1Boise, Idaho, United States · DRAM wafers
Hwaseong and Giheung line conversionsHwaseong, Gyeonggi, Korea · DRAM wafers
Converting
2025–2027Legacy DRAM lines converted to 1b/1c
—
Included in the industry baseline
2 points · 1 sources▮▮▯medium
Samsung
Pyeongtaek P1/P2 and Hwaseong V-NAND linesPyeongtaek and Hwaseong, Gyeonggi, Korea · NAND wafers
Converting
2026V10 400+-layer ramp
22025
≈Assumedwithheld
3 points · 1 sources▮▮▯medium
SK hynix
Cheongju M15 and Icheon NAND linesCheongju and Icheon, Korea · NAND wafers
Converting
Jan 20262026 NAND investment, conversion only
22025
≈Assumedwithheld
3 points · 1 sources▮▮▯medium
Operating, part of the baseline 9 sites already in the baseline
Fab register: the operating sites already in the baseline, with status, next milestone, capacity blocks, wafer starts, and evidence count
Maker
Site
Status
Next milestone
Blocks · first year
Wafer starts · licensed
Evidence
Operating, part of the baseline 9
Kioxia/Sandisk
Yokkaichi Fab7Yokkaichi, Mie, Japan · NAND wafers
Operating
2025BiCS8 volume at Yokkaichi
12025
Included in the industry baseline
3 points · 1 sources▮▮▮high
Micron
Taichung and Taoyuan DRAM fabs; Taichung HBM assemblyTaichung and Taoyuan, Taiwan · DRAM wafers
Operating
2024–2026HBM3E assembly and test expansion
12025
≈Assumedwithheld
2 points · 1 sources▮▮▯medium
Others
Nanya, Winbond, PSMC and othersTaiwan and others, Taiwan · DRAM wafers
Operating
2026–2027Nanya new fab (Fab 3) phase 1 tool move-in
12025
Included in the industry baseline
1 points · 1 sources▮▯▯low
Samsung
Pyeongtaek P3Pyeongtaek, Gyeonggi, Korea · DRAM + NAND wafers
Operating
2023–2026DRAM phases equipped (reported)
12025
≈Assumedwithheld
2 points · 1 sources▮▯▯low
Samsung
Xi'an V-NANDXi'an, Shaanxi, China · NAND wafers
Operating
Dec 2025VEU revocation effective, with annual licenses thereafter
12025
≈Assumedwithheld
3 points · 1 sources▮▮▯medium
SK hynix
Icheon M14 and M10 DRAM floorsIcheon, Gyeonggi, Korea · DRAM wafers
Operating
2025–2027M10 legacy DDR4 wind-down
32025 · base
Included in the industry baseline
3 points · 1 sources▮▮▯medium
SK hynix
M16Icheon, Gyeonggi, Korea · DRAM wafers
Operating
2024–2026EUV 1a/1b conversions
12025
Included in the industry baseline
2 points · 1 sources▮▮▮high
SK hynix
Solidigm Dalian Fab 1 / Fab 2Dalian, Liaoning, China · NAND wafers
Operating
Dec 2025VEU revocation effective
12025
≈Assumedwithheld
2 points · 1 sources▮▮▯medium
SK hynix
Wuxi C2 / C2FWuxi, Jiangsu, China · DRAM wafers
Operating
Dec 2025VEU revocation effective
12025
≈Assumedwithheld
3 points · 1 sources▮▮▯medium
11 of 31 records are at low confidence: Pyeongtaek P4, Pyeongtaek P5, Idaho ID2, New York megafab, Fab 1, Hefei DRAM fabs, Wuhan NAND fabs, Cheongju P&T7 advanced packaging, Pyeongtaek P3, Yongin national industrial complex (Cheoin), Beijing fab, Nanya, Winbond, PSMC and others.
China
CXMT gets to 14.4% of the industry's wafers and 8.3% of its bits.
Wafers are the easy part of Chinese DRAM: cleanrooms, DUV tools bought before the export controls, and domestic deposition and etch tools. Bits are the hard part. Without EUV, and with export licences required for tools that make DRAM at 18 nm half-pitch or below, the node ladder stops near 1α-equivalent. So each wafer holds fewer bits than the industry average, and the gap widens as the leading edge moves to 1γ and 1δ. The three tool scenarios below run through the same blocks.
CXMT share of industry DRAM wafer starts and of bitsPercent of industry
Share of wafer starts Share of bits Wafers that carry fewer bits because of the node ceiling
CXMT capacity, wafer starts, and bits under three tool scenarios
Scenario
2025
2027E
2030E
Base: domestic tools plus pre-control DUV≈AssumedHefei and Beijing reach ≈310k wpm by 2027 and ≈370k by 2030. G5 (1α-equivalent) becomes the majority node by 2028. No EUV.
240k197k started · 2.6 EB
310k279k started · 4.2 EB
370k333k started · 5.3 EB
Tool-constrained: additions halved, node frozen≈AssumedAccess to immersion DUV, etch, and deposition tools tightens. Additions run at half the base case and the node mix stays at the 2024 G4/G5 split.
218k178k started · 2.0 EB
253k227k started · 2.7 EB
283k254k started · 3.1 EB
Unconstrained: reported path○ReportedAdditions at 160% of the base case, reaching the ≈380k wpm that the reported series shows for 2027, with the same node ladder as the base case.
267k219k started · 2.9 EB
379k341k started · 5.1 EB
475k428k started · 6.8 EB
The table shows installed capacity, wafers started, and sellable bits as annual averages. The unconstrained scenario reproduces the reported path (the published forecast, 380k wpm in 2027). The base case holds CXMT to what domestic tools and DUV tools bought before the controls can equip. 8 evidence points support this, including the October 2022 and December 2024 BIS rules and YMTC's Entity List designation.
Evidence and assumptions
Every number is disclosed, derived, assumed, or reported, and we never blend the four.
173 data points sit behind this build. 65 are disclosed by a maker or government. 11 are derived, with the arithmetic shown. 20 are our own assumptions, each with a range and what would change it. 77 are reported by third-party research and used only for comparison. 14 are marked low confidence.
•DisclosedƒDerived≈Assumed○Reported
•Disclosed▮▮▯mediumSamsung Electronics · 2022≈20% more bits per wafer
Samsung 12nm-class DDR5 wafer productivity versus prior node
Dec 21, 2022 · Newsroom release: productivity improvement of about 20% over the previous node
A wafer-level number, so we can use it directly. It is the only disclosed per-node wafer-productivity anchor we have collected (SK hynix's 1c release quantifies speed rather than productivity). Our assumed per-node wafer gain of ≈15–20% sits at or below it, and well below vendors' 30–40% array-density claims.
Apr 24, 2024 · Newsroom release: ₩5.3T for fab construction beginning late April 2024; completion targeted November 2025; cumulative investment above ₩20T; HBM-focused DRAM
The shell budget is disclosed. The tool budget and wafer-start plan are not. The model's 80k wafers-per-month peak is a Joule14 assumption.
≈Assumed▮▮▯mediumIndustry · 2025≈1.97M wafers per month installed, ≈1.79M started
Industry DRAM wafer capacity
Joule14 analysis
Joule14 · Fab Ledger capacity roll-up
Aug 28, 2026 · Sum of the fab capacity blocks, 2024 annual average: Samsung ≈680k, SK hynix ≈510k (incl. Wuxi ≈155k), Micron ≈340k, CXMT ≈205k, others ≈115k = ≈1.85M installed at ≈87% utilization; cross-checked against reported wafers out
Range 1.87M wpm to 2.07M wpm
No vendor discloses wafer starts. The fab capacity blocks record installed capacity and utilization separately, so 100k wpm of capacity never becomes 100k wafers started. The 2026 figure is derived from the same blocks.
Mar 20, 2024 · Prepared remarks: HBM3E consumes approximately three times the wafer supply of DDR5 to produce a given number of bits in the same node
This is the single most important supply-side conversion factor. Larger die, TSV area, stacking and test yield all consume wafers that never become shipped bits.
ƒDerived▮▯▯lowIndustry · 2026≈3.1–3.4 TB per wafer by maker
Good bits per wafer, 1c-class 24Gb
Joule14 analysis
Joule14 · Fab Ledger wafer-to-bit arithmetic
Aug 28, 2026 · lib/memory-supply/math.ts bitsPerWaferGb()
When the same wafer goes into HBM4 stacks, we divide by the wafer multiplier. That gives about 1.1 TB of shipped HBM bits per wafer at 3.1×.
ƒDerived▮▮▯mediumIndustry · 2025–2030E3.0× (2024–2025) → 3.1× (2026E) → 3.2× (2027E+), plus a Samsung block scale while its HBM qualifies
Blended HBM wafer multiplier used in the model
Joule14 analysis
Joule14 · Fab Ledger HBM conversion
Aug 28, 2026 · lib/memory-supply/math.ts hbmWaferPenaltyPoints()
Derivation Start from Micron's ≈3× HBM3E statement (ev-mu-hbm-multiplier). Step up as HBM4's larger core dies and 12–16-high stacks enter the mix (ev-mu-hbm4-multiplier, ev-sec-hbm4). Blend by the assumed HBM3E/HBM4 shipment mix per year.
We apply the multiplier to the HBM wafer starts of each fab capacity block, so it sets the size of the HBM wafer drain in the bridge, the breakdown of where each year's growth comes from. HBM rising from 7.3% to 10.8% of bits, with the multiplier moving from 3.0× to 3.1×, takes 4.6 points off 2026 industry bit growth. The +0.5× sensitivity in the assumptions register shows the effect of a higher ratio.
•Disclosed▮▮▯mediumMicron · 2H 2027Second half of 2027
Jun 12, 2025 · ID1 timeline: first DRAM wafer output expected in the second half of calendar 2027
First output is not full output. The model ramps ID1 across 2028–2029 and treats the 2027 contribution as immaterial to industry bits.
•Disclosed▮▮▮highIndustry · 2022-10-07Licence requirement for tools making DRAM at 18 nm half-pitch or below and NAND at 128 layers or more in China
BIS advanced-node equipment controls for China
Government record
U.S. Department of Commerce, Bureau of Industry and Security · Implementation of Additional Export Controls: Certain Advanced Computing and Semiconductor Manufacturing Items
Oct 7, 2022 · Interim final rule; DRAM 18 nm half-pitch and NAND 128-layer thresholds; presumption of denial for Chinese-headquartered fabs
This is the threshold that caps CXMT's node ladder at roughly 1z/1α-equivalent without EUV and YMTC's at what domestic and pre-control tools can process.
UBS Global Research · Memory Semis Monthly, September '26 Edition: Substantial unfulfilled demand ahead
Aug 30, 2026 · Figures 3–10, 31–36, 41–42; supply/demand summaries and vendor tables
This is a shipments series, so it includes inventory movements that our production series does not. The 2026E figure needs roughly +18% bits per wafer out. See the comparison with published forecasts.
UBS Global Research · Memory Semis Monthly, September '26 Edition: Substantial unfulfilled demand ahead
Aug 30, 2026 · Figures 3–10, 31–36, 41–42; supply/demand summaries and vendor tables
Our model has 205k → 240k → 290k → 310k. The 2027 gap is the tool-constraint question that the China section works through.
In the licensed version+163 more data points
The licensed version lists every fab, capex program, node, and HBM parameter, each with its source, derivation, or range. You can export them with their evidence ids.
The 6 assumptions we set, with their range and what would change them
Assumptions register
Assumption
Base case
Range
What would change it
HBM wafer multiplier ƒDerived5 points of evidence
3× in 2025, rising to 3.2× by 2027 and held there. We use Micron's disclosed path (about 3:1 for HBM3E, higher for HBM4, above 4:1 for HBM4E) for the +0.5× sensitivity rather than the base case, because we set the base case so that HBM bits match the published shipments
2.5× to 4.0×
A vendor disclosing an HBM4 trade ratio, or measured stack-yield improvement that shrinks the gap to standard DRAM. A ten-point gain in known-good-stack yield lowers the multiplier by roughly 0.35×. Micron has said the ratio rises from about 3 toward 4 across HBM3E, HBM4, and HBM4E.
HBM share of DRAM wafer starts ≈Assumed5 points of evidence
HBM shares set for each fab capacity block, which add up to 23.1% of wafers (10.8% of bits) in 2026 and 30.5% (16.1%) in 2030
±3 points of wafer share in any year
HBM TAM guidance changes, accelerator unit forecasts, a vendor reallocating a named fab, or HBM pricing per bit falling faster than we assume.
Node ladder and migration pace, DRAM ≈Assumed7 points of evidence
Good bits per wafer for each node come from our node table, and each maker's node mix moves along its own schedule. This adds up to +9.6 pts in 2026 and +4.2 pts in 2030
75% to 125% of the node ladder's pace
EUV tool availability, 1c/1d yield disclosures, or a vendor pausing conversions to protect HBM output.
Utilization (wafer starts ÷ installed capacity) ≈Assumed4 points of evidence
DRAM 85% (2024) → 93% (2026). NAND 76% → 83% (2027). New fabs at 70% while they ramp
±2 points
Disclosed wafer-start cuts or restorations, inventory weeks, or a maker stating its loading.
Cleanroom completion to full output ≈Assumed3 points of evidence
12–18 months. New fab capacity blocks start at 70% utilization
12 to 24 months
Tool lead times, hiring, or a vendor disclosing first-wafer-out for a named fab.
China wafer additions ≈Assumed4 points of evidence
50% to 160% of the additions (the scenarios in the China section)
CXMT listing disclosures, export-control changes, or observed tool-import data.
What moves our figures most
Node migration pace: Node gains at 75% of the pace in our node ladder. 2026 growth 2.2 points lower, 2028 growth 1.2 points lower, and the 2030 DRAM index 8.0% lower.
HBM wafer shift lands later: −4 pts of HBM share in 2024–2025 only, then back to the base case. 2026 growth 2.8 points lower, 2028 growth unchanged, and the 2030 DRAM index 2.3% lower.
Yongin Fab 1 and P5: One-year slip. 2026 growth unchanged, 2028 growth 0.6 points lower, and the 2030 DRAM index 2.3% lower.
HBM wafer multiplier: +0.5× from 2026. 2026 growth 1.7 points lower, 2028 growth 0.2 points lower, and the 2030 DRAM index 2.2% lower.
HBM share of wafer starts: +3 pts from 2026 wherever HBM is made. 2026 growth 2.2 points lower, 2028 growth 0.1 points lower, and the 2030 DRAM index 2.2% lower.
These are the five of the nine DRAM re-runs of the model that move the 2030 DRAM index most. All ten re-runs, DRAM and NAND, are in the licensed workspace.
How this works
From cleanroom to sellable bits, with the evidence shown at every step.
Installed capacity is not the same as wafer starts, so each block has its own utilization figure. Bits per wafer come from die area, die density, and yield by node. We track HBM in both wafers and bits, so the wafers it uses up are never hidden inside a bit total. The band and the sensitivities are the same blocks re-run with changed inputs.
Filings: SEC 10-Q and 10-K, Korean DART facility-investment filings, Japanese securities reports, METI and CHIPS award records, BIS rules.
Permits and utilities: environmental statements, construction permits, power and water allocations that bound a site's wafer starts years ahead.
Equipment vendors: EUV shipments, bonder and tester contracts, lead times, China tool imports.
Third-party research: we log it as reported points for comparison and never use it as an input.
How we check it
Each quarter we compare the block-level model with the makers' reported bit growth and with published forecasts. We print the gaps with the blocks that explain them. When a gap calls for a revision, we change the block with the weakest evidence first and never a disclosed one. Every bridge shows its rounding residual.
What the license adds
The public page shows the industry totals. The license opens every fab capacity block.
There is one institutional license. We license it by request so the founding cohort stays small enough to brief every quarter. What it adds is detail, and the table below states that detail in counts we can stand behind.
What the license adds, public versus licensed
Public
Licensed
Fab records opened in full
1 of 31
All 31, with every milestone and source
Capacity blocks with installed → starts → output paths
1 of 35
All 35 blocks, by year, with node and product mix
Wafer-start estimates, each with how it is backed up
1 sites
18 sites
Company-level supply series
Industry only
7 makers, DRAM and NAND, bits, wafers, HBM share
Growth bridges
2025 → 2026
Every year to 2030 (6 per product)
Evidence points with full citation
10 of 173
All 173, exportable with ids
Scenario re-runs
Low–high band and the 5 DRAM re-runs that move the 2030 DRAM index most
All 10 re-runs, DRAM and NAND, and any set of overrides on the assumptions register, re-run on request
The full ledger, exported
Every fab record and capacity block, with its installed-capacity, utilization, node-mix, and product-mix paths. Every evidence point with its citation. Company and industry series. Every yearly bridge. Delivered as CSV and JSON, keyed by record and evidence id, and regenerated with each revision.
Quarterly revisions and a briefing
A revision after each earnings cycle with a row-level diff of what moved and why, and a 30–45 minute analyst briefing on what changed.
Scenario re-runs
Your own overrides on the assumptions register (ramp slips, node pace, China, HBM share, utilization), re-run through the same model and returned as series and bridges.
Interim notes between revisions
A note when a disclosure changes the first-output date, capacity, or status of a fab capacity block we track, with the document that changed it. Written and sent by hand rather than by a system.
Shape
Annual license, per firm
Seats
Up to five named seats
Founding cohort
Ten firms in the founding cohort. That is the number of firms Joule14 can brief each quarter.
Price
Quoted on request. The founding price is held through the first renewal. One annual figure per firm, with no per-seat or per-module add-ons.
Use
Internal use, including feeding your own models. You may quote it with attribution. No redistribution outside the firm.
Firms whose decisions depend on how many memory bits can be made: investors and analysts who cover the memory makers, their equipment suppliers, and their customers, and the planning teams at companies whose products depend on memory. The license is per firm. Individual readers are best served by the public page and the research library.
What does fab by fab mean?
We model each fab capacity block on its own. A block is a phase, a cleanroom, or a capacity block with its own paths for installed capacity, utilization, node mix, and product mix. Industry and company figures are the sum of the blocks, so every figure can be traced back to the sites that produce it.
How is this different from published forecasts?
Published forecasts sit next to our figures, marked reported, and never become an input to the model. Where our figure differs from the published median by three points or more, we explain the gap and name the fab capacity blocks that account for it.
How often does it change?
Revised every quarter. Data points updated as disclosures land. Each revision comes with a row-level diff of what moved and why. Before the model speaks about the next year, we check that it reproduces the last reported year, and we print the differences that remain.
What does the license cost?
Quoted on request. The founding price is held through the first renewal. One annual figure per firm, with no per-seat or per-module add-ons. Pro-rated cancellation within 60 days. Up to five named seats, for internal use including your own models.
Is this investment advice?
No. Fab Ledger describes what can be produced. It does not say what will be sold or at what price, and it makes no individualized investment recommendations. Company names show which fabs we cover. They are never ratings.
What happens after I request access?
Joule14 replies within three business days with the license terms in writing, the current model scope, as shown on this page, the CSV and JSON exports of the fab records and evidence ledger, and a briefing slot, if you ask for one. Every request is read by the analyst who maintains the model. No payment information is collected, and requesting access creates no purchase obligation.
Request the ledger
Tell us which decisions the model needs to inform.
Joule14 replies within three business days with the license terms in writing, the current model scope, as shown on this page, the CSV and JSON exports of the fab records and evidence ledger, and a briefing slot, if you ask for one.
Every request is read by the analyst who maintains the model. There is no automated sales sequence.
No payment information is collected here.
The license is per firm. Individual readers are best served by the public page and the research library.
Fab Ledger is built and revised from primary documents: earnings calls, filings, permits and utility allocations, equipment disclosures, and export-control rules. Third-party research is collected for comparison and never used as an input. Each revision is published with a row-level diff of what moved and why.
No vendor sponsorship and no paid placement. Company names appear only as coverage. They are not ratings.
Latest revision
R2.6 · LS Securities' supply model loaded
We loaded LS Securities' 25 August 2026 report, the first published bottom-up DRAM supply model we have read that runs to 2030. It gives wafer capacity by fab for Samsung, SK hynix, Micron and CXMT to 2033, three-maker and industry bit growth to 2033 with the node-migration share split out, a node roadmap with 1d slipping to 2028, and a 2027 HBM bit supply assumption. Its industry DRAM bit growth for 2028 to 2030 rests on wafer capacity growing 17 to 18 percent a year, while its node-migration gain is close to ours. So the published forecasts no longer stop at 2027: for 2028 to 2030 there is one firm's figure, and the pages now say so instead of saying there is none.
Figures added, all read in the report itself: DRAM bit supply growth 2025–2030, DRAM wafer capacity growth 2025–2030 (a new measure, compared with our installed capacity), CXMT wafer capacity 2025–2030, and HBM bit growth 2027.
Evidence added and linked from the fab records: LS Securities' wafer capacity schedules for Samsung P4, P5 and Yongin; SK hynix M15X, Yongin 1 and 2 and Cheongju M17; Micron ID1, ID2, New York and Singapore; CXMT Shanghai, Hefei and Beijing; plus its node roadmap, its cell-area table and its node-migration series.
The horizon note, the path strip and the CSV now distinguish the years with two or more published forecasts (to 2027) from the years with one (2028 to 2030).
Earlier: R2.5, R2.3, R2.2, R2.1, R2, R1. The full log, with every change, is in the licensed workspace.
Next: R3 · January 2027
We revise after the reported figures listed under what tests this, or when a maker restates the first-output date for a block.
2026.3 · R2 bottom-up build · +13.3% 2026E DRAM base case · revised every quarter. data points updated as disclosures land
